PIC18F4539-E/PT【PDF 86/322 页】IC PIC MCU FLASH 12KX16 44TQFP

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PIC18FXX39

DS30485A-page 174

Preliminary

2002 Microchip Technology Inc.

17.2.2

USART ASYNCHRONOUS

RECEIVER

The receiver block diagram is shown in Figure 17-4.

The data is received on the RC7/RX/DT pin and drives

the data recovery block. The data recovery block is

actually a high speed shifter operating at x16 times the

baud rate, whereas the main receive serial shifter oper-

ates at the bit rate or at FOSC. This mode would

typically be used in RS-232 systems.

To set up an Asynchronous Reception:

Initialize the SPBRG register for the appropriate

baud rate. If a high speed baud rate is desired,

set bit BRGH (Section 17.1).

Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

If interrupts are desired, set enable bit RCIE.

If 9-bit reception is desired, set bit RX9.

Enable the reception by setting bit CREN.

Flag bit RCIF will be set when reception is com-

plete and an interrupt will be generated if enable

bit RCIE was set.

Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

Read the 8-bit received data by reading the

RCREG register.

If any error occurred, clear the error by clearing

enable bit CREN.

10. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

17.2.3

SETTING UP 9-BIT MODE WITH

ADDRESS DETECT

This mode would typically be used in RS-485 systems.

To set up an Asynchronous Reception with Address

Detect Enable:

Initialize the SPBRG register for the appropriate

baud rate. If a high speed baud rate is required,

set the BRGH bit.

Enable the asynchronous serial port by clearing

the SYNC bit and setting the SPEN bit.

If interrupts are required, set the RCEN bit and

select the desired priority level with the RCIP bit.

Set the RX9 bit to enable 9-bit reception.

Set the ADDEN bit to enable address detect.

Enable reception by setting the CREN bit.

The RCIF bit will be set when reception is com-

plete. The interrupt will be acknowledged if the

RCIE and GIE bits are set.

Read the RCSTA register to determine if any

error occurred during reception, as well as read

bit 9 of data (if applicable).

Read RCREG to determine if the device is being

addressed.

10. If any error occurred, clear the CREN bit.

11. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and interrupt the CPU.

FIGURE 17-4:

USART RECEIVE BLOCK DIAGRAM

x64 Baud Rate CLK

SPBRG

Baud Rate Generator

RC7/RX/DT

Pin Buffer

and Control

SPEN

Data

Recovery

CREN

OERR

FERR

RSR Register

MSb

LSb

RX9D

RCREG Register

FIFO

Interrupt

RCIF

RCIE

Data Bus

÷ 64

÷ 16

STOP

START

(8)

RX9

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